1. Field of the Invention
The present invention relates to an NAND-circuit-type address decoder apparatus for decoding address signals, more particularly to an address decoder apparatus composed of CMOS using P- and N-channel MISFETs.
2. Description of the Related Art
An address decode circuit for use in semiconductor memories comprises a P-channel logical block including P-channel enhancement-type MISFETs and a N-channel logical block including N-channel enhancement-type MISFETs.
FIG. 6 shows the configuration of an existing address decoder having the P-channel logical block 51 and N-channel logical block 52. In this decoder the power-supply voltage V.sub.DD of positive polarity is applied to the P-channel logical block 51, and the reference voltage V.sub.SS of 0 volt is applied to the N-channel-logical block 52. Address signals AO-An are supplied to the logical blocks 51 and 52 through input wires 53 in parallel. The address signals are supplied to the gates of MISFETs of the P-channel logical block 51 and the N-channel logical block 52.
The output wires extending from the P-channel-side logical block 51 and the N-channel-side logical block 52 are arranged in the wiring space between the logical blocks 51 and 52, and are connected with output wires 54 in this space.
The address decoder, thus configured, is a so-called NAND circuit system, in which P-channel MISFET circuits formed by connecting P-channel MISFETs in parallel are installed in the P-channel logical block 51, and N-channel MISFET circuits formed by connecting N-channel MISFETs in series are installed in the N-channel logical block 52. A set of local decode circuit is formed of a set of MISFET circuit of the P-channel logical block 51 and a set of MISFET circuit of the N-channel logical block 52. Thus, the address decoder is made by combining local decode circuits.
FIG. 7 shows a one of the local decode circuits constituting the address decoder, to which 2-bit address signals IN1 and IN2 are input.
The P-channel MISFET circuit in the P-channel logical block 51 is composed of two P-channel MISFETs QP1 and QP2 which are connected in parallel between the output node and the point where the supply voltage V.sub.DD is input. The N-channel MISFET circuit in the N-channel logical block 52 is composed of two N-channel MISFETs QN1 and QN2 which are connected in series between the output node and the point where the reference voltage V.sub.SS is input. The address signal IN1 is supplied to the gates of the P-channel MISFET QP1 and the N-channel MISFET QN1 and the address signal IN2 is supplied to the gates of the P-channel MISFET QP2 and the N-channel MISFET QN2. Output signals are output from the output nodes of P-channel and N-channel MISFET circuits.
FIG. 8 show the address decoder actually mode in the form of an integrated circuit. FIG. 8 illustrates, in particular the elements of the P and N channel logical blocks shown in FIG. 6.
Power-supply voltage wire 61 made of aluminum, to which the supply voltage V.sub.DD is set, and the supply voltage wire 62 made of aluminum to which the reference voltage V.sub.SS is set, extend parallel and vertically in FIG. 8. P-type diffusion areas 63, 64, and 65, which serve as the source and drain areas of the P-channel MISFETs QP1 and QP2, are formed and connected to the wire 61 to which the supply voltage V.sub.DD is set. N-type diffusion areas 66 and 67, which serve as the source and drain areas of the N-channel MISFETs QN1 and QN2, and the N-type diffusion area 68, which serve as a part of the output wire, are formed and provided for the supply voltage wire 62 to which the supply voltage V.sub.CC is set. Polycrystal silicon wires 69 and 70 are formed as the gate electrodes of the MISFETs QP1, QP2, QN1, and QN2, to which signal wires 71 and 72 made of aluminum and extending formed parallel to the wires 61 and 62 are connected. The input signals IN1 and IN2 are supplied to the signal wires 71 and 72. Jumper wire 73 made of aluminium connects the P-type diffusion area 64, which serves as the drain area common to the P-channel MISFETs QP1 and QP2, to the N-type diffusion area 68 which serves as the drain area of the N-channel MISFET QN1.
Many local decode circuits, in FIG. 8, are formed on one semiconductor chip. Signal wires for supplying address signals to many local decode circuits should be formed outside the logical blocks. Therefore, a large wire area is necessary for the signal wires. Since the address decoder is a combination of many local decode circuits, the layout of the local decode circuits is complicated in proportion to memory capacity.
To obtain output signals from many local decode circuits, jumper wires must be arranged in the logical blocks. Thus, when the area of each local decode circuit increases, especially when the number of address-signal bits is large because of an increase of memory capacity, the area required for each local decode circuit will increase.